Technical Lead - ASIC IP verification

Technical Lead - ASIC IP verification

About Us:

At Quality Assistance Sweden AB, we specialize in connecting top talent with leading global companies. We are currently seeking an experienced Senior Technical Lead to drive innovation and shape the future of telecommunication through joining our client's team.

Who Will You Work With:

Our client is a leading semiconductor and technology innovator, pushing the boundaries of co-design approach across silicon, hardware, and software. You will be working with a highly skilled verification team focused on developing and validating complex ASIC designs.

About the Role:

As a Technical Lead, you will:

• Craft and execute top-notch verification plans, ensuring every detail is covered.
• Design and refine cutting-edge verification environments for peak performance.
• Develop and maintain UVCs, leaving no design corner unverified.
• Lead both random and directed testing strategies to catch elusive bugs.
• Utilize advanced coverage techniques to achieve exceptional verification completeness.
• Drive continuous innovation, enhancing product quality, efficiency, and workflows.

Key Responsibilities:

• Perform ASIC verification tasks focusing on the Client telecommunications requirement.
• Implement and execute testbenches and verification environments using System-Verilog and UVM (Universal Verification Methodology).
• Integrate and verify VIPs (Verification IP) in larger sub-systems.
• Conduct GLS (Gate Level Simulations) to ensure timing and functionality.
• Collaborate with cross-functional teams to deliver high-quality, verified RTL (Register Transfer Level).
• Utilize GIT for version control and collaborate in a structured codebase environment.
• Communicate effectively and contribute to continuous improvement initiatives within the team.
• Lead and mentor new graduates.

Required Skills (Must-have):

• 10+ years of hands-on experience in ASIC verification, preferably within Client-based systems.
• 5+ years of advanced ASIC and/or FPGA verification at IP, sub-system, and chip levels, using System-Verilog UVM
• 5 years’ experience in Cadence and Synopsys verifications tools.
• Very high-level know-how and confidence using delivery and deployment testbenches.
• Hands-On experience designing UVM test environments and driving coverage closure.
• Ready to learn something new daily and apply it to make a real difference.
• Creative problem-solving skills — you see challenges as opportunities for innovation.
• Collaborative spirit and the ability to thrive both independently and in team
• Exceptional communication skills in English, both written and oral.
• Results-oriented mindset with a passion for continuous improvement, always seeking more innovative, faster and high-quality solutions.
• Master’s degree in Electrical Engineering, Computer Engineering, or a related field

What We Offer:

• Impactful Work: Contribute to the development of next-generation semiconductor technologies.
• Contract Type: 2 years contract with possibility of extension.
• Work location: Stockholm, Sweden on-site (no remote option available)

This is employment is open to candidates across the EU/EES and Switzerland

Interview Process:

The selection process typically includes one or two technical interview rounds, followed by a discussion with project stakeholders.

How to Apply:

Please send your application to fawziashraf608@gmail.com. Please note that your application must include a resume that meets all ‘must-have’ requirements and a cover letter listing at least 2 (two) references.