Publicerad: 2025-11-05
Developer ASIC
Ericsson AB
Join our Team
About this opportunity:
Are you driven by innovation and ready to influence the next generation of high-performance ASICs? We are seeking a Senior ASIC Design Engineer who combines deep technical mastery with a strategic, big-picture mindset. This is a role for someone who thrives in designing for today while envisioning tomorrow—someone who sees technology not just as circuits, but as platforms for future growth.
You will be part of a collaborative, forward-looking team where your expertise will guide both current projects and the architectural direction of upcoming designs. We’re scaling for the future—this is your chance to leave a legacy at Ericsson that truly lasts.
What You Will Do
• Architect and implement advanced ASIC IP and subsystems enabling next-generation wireless solutions.
• Own RTL design and verification at block and subsystem levels, driving quality from concept through tape-out.
• Collaborate closely with verification, physical design, and system teams to ensure robust integration and performance.
• Document architectures, define design specifications, and propose enhancements for scalability and sustainability.
• Lead process improvements and champion automation to increase design efficiency.
• Mentor engineers and foster a culture of knowledge sharing and technical excellence.
Skills You Bring
• Expertise in RTL design and microarchitecture using Verilog/SystemVerilog, including FSMs, pipelines, and clocking.
• Good understanding of functional verification methodologies, including SystemVerilog and UVM.
• Good ability to collaborate with verification teams to develop test plans, assertions, and coverage models.
• Experience with simulators such as VCS, Questa, and ModelSim for thorough verification and debugging.
• Proficiency in logic synthesis (Synopsys Design Compiler, Cadence Genus) and timing closure with PrimeTime.
• Experience defining chip-level architecture, including block diagrams, AXI/PCIe/Ethernet protocols, memory hierarchies, and DMA engines.
• Knowledge of low-power design techniques (UPF/CPF), DFT methods (scan chains, MBIST), and PPA trade-offs.
• Skilled in scripting languages (Python, Tcl, Perl) for design automation and system-level modeling.
• Excellent communication skills, with leadership in cross-functional teams and mentoring junior engineers
Join our Team
About this opportunity:
Are you driven by innovation and ready to influence the next generation of high-performance ASICs? We are seeking a Senior ASIC Design Engineer who combines deep technical mastery with a strategic, big-picture mindset. This is a role for someone who thrives in designing for today while envisioning tomorrow—someone who sees technology not just as circuits, but as platforms for future growth.
You will be part of a collaborative, forward-looking team where your expertise will guide both current projects and the architectural direction of upcoming designs. We’re scaling for the future—this is your chance to leave a legacy at Ericsson that truly lasts.
What You Will Do
• Architect and implement advanced ASIC IP and subsystems enabling next-generation wireless solutions.
• Own RTL design and verification at block and subsystem levels, driving quality from concept through tape-out.
• Collaborate closely with verification, physical design, and system teams to ensure robust integration and performance.
• Document architectures, define design specifications, and propose enhancements for scalability and sustainability.
• Lead process improvements and champion automation to increase design efficiency.
• Mentor engineers and foster a culture of knowledge sharing and technical excellence.
Skills You Bring
• Expertise in RTL design and microarchitecture using Verilog/SystemVerilog, including FSMs, pipelines, and clocking.
• Good understanding of functional verification methodologies, including SystemVerilog and UVM.
• Good ability to collaborate with verification teams to develop test plans, assertions, and coverage models.
• Experience with simulators such as VCS, Questa, and ModelSim for thorough verification and debugging.
• Proficiency in logic synthesis (Synopsys Design Compiler, Cadence Genus) and timing closure with PrimeTime.
• Experience defining chip-level architecture, including block diagrams, AXI/PCIe/Ethernet protocols, memory hierarchies, and DMA engines.
• Knowledge of low-power design techniques (UPF/CPF), DFT methods (scan chains, MBIST), and PPA trade-offs.
• Skilled in scripting languages (Python, Tcl, Perl) for design automation and system-level modeling.
• Excellent communication skills, with leadership in cross-functional teams and mentoring junior engineers